EE316 Digital Logic Design Lab 218 Sep 2016
Design an excess-3 code converter to drive a seven-segment indicator. The four inputs to the converter circuit (A, B, C, and D in Figure 8-15) represent an excess-3 coded decimal digit. Assume that only input combinations representing the digits 0 through 9 can occur as inputs, so that the six unused combinations are don’tcares. Design your circuit using only two-, three-, and four-input NAND gates and inverters. Try to minimize the number of gates and inverters required. The variables A, B, C, and D will be available from toggle switches. Use (not ) for 6. Use (not ) for 9. Any solution with 16 or fewer gates and inverters (not counting the four inverters for the inputs) is acceptable.