Joseph Bae Computer Engineering Student @ The University of Texas at Austin

EE316 Digital Logic Design Lab 3 Part 2

(a) Using a 3-to-8 decoder and two four-input OR gates, design a circuit that has three inputs and a 2-bit output. The output of the circuit represents (in binary form) the number of 1’s present in the input. For example, when the input is ABC = 101, the output will be Count = 10. Write an entity-architecture pair to implement a 3-to-8 decoder. Then write an entity-architecture pair for your circuit, using the decoder as a component. Use the port definitions specified below. For the 3-to-8 decoder: port (a, b, c: in bit; y0, y1, y2, y3, y4, y5, y6, y7: out bit); For the main circuit: port (a, b, c: in bit; count: out bit_vector (1 downto 0)); (b) Simulate your code and test it using the following inputs: a b c = 0 0 0, 0 1 0, 1 1 0, 1 1 1, 0 1 1

    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity decoder is
    port( a, b, c: in std_logic;
    y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end decoder;
architecture arch1 of decoder is
begin
    y0 <= (not a) and (not b) and (not c);
    y1 <= (not a) and (not b) and c;
    y2 <= (not a) and b and (not c);
    y3 <= (not a) and b and c;
    y4 <= a and (not b) and (not c);
    y5 <= a and (not b) and c;
    y6 <= a and b and not c;
    y7 <= a and b and c;
end arch1;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity full_adder is
    port(a, b, c: in std_logic; output: out std_logic_vector (1 downto 0));
end full_adder;
architecture arch2 of full_adder is
    component decoder
    port (a, b, c: in std_logic;
    y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end component;
signal z0, z1, z2, z3, z4, z5, z6, z7: std_logic;
begin
    decoder0: decoder
    port map (a, b, c, z0, z1, z2, z3, z4, z5, z6, z7);
    output(0) <= (z1 or z2 or z4 or z7);
    output(1) <= (z3 or z5 or z6 or z7);
end arch2;