Joseph Bae Computer Engineering Student @ The University of Texas at Austin

EE316 Digital Logic Design Lab 6

Write a VHDL module for a 4-bit counter with enable that increments by different amounts, depending on the control input C. If En = 0, the counter holds its state. Otherwise, if C = 0, the counter increments by 1 every rising clock edge, and if C = 1, the counter increments by 3 every rising clock edge. The counter also has an activelow asynchronous preset signal, PreN.

Part 1

    
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab5_part1 is
port (CLK, PreN, En, C: in std_logic;
Qout: out std_logic_vector (3 downto 0));
end lab5_part1;
architecture counter of lab5_part1 is
signal Q: std_logic_vector (3 downto 0);
begin
Qout <= Q;
process (PreN, CLK)
begin
if PreN = '0' then Q <= "1111";
elsif CLK'event and CLK = '1' then
if En = '0' then Q <=Q;
elsif En = '1' and C = '0' then Q <= Q + 1;
elsif En = '1' and C = '1' then Q <= Q + 3;
end if;
end if;
end process;
end counter;
    

EE Lab 6 Wave Diagram

Part 2

    
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lab6_part2 is
port (X, CLK: in bit;
Z: out bit);
end lab6_part2;
architecture Table of lab6_part2 is
signal State, Nextstate: integer range 0 to 5:=0;
begin
process (State, X)
begin
case State is
when 0 =>
if X = '0' then Z <='0'; Nextstate <= 1;
else Z <= '0'; Nextstate <= 3; end if;
when 1 =>
if X = '0' then Z <= '0'; Nextstate <= 3;
else Z <= '0'; Nextstate <=2; end if;
when 2 =>
if X = '0' then Z <='0'; Nextstate <= 4;
else Z <= '0'; Nextstate <= 2; end if;
when 3 =>
if X = '0' then Z <= '0'; Nextstate <= 3;
else Z <= '0'; Nextstate <=5; end if;
when 4 =>
if X = '0' then Z <='1'; Nextstate <= 3;
else Z <= '0'; Nextstate <= 2; end if;
when 5 =>
if X = '0' then Z <= '1'; Nextstate <= 4;
else Z <= '0'; Nextstate <=2; end if;
end case;
end process;
process (CLK)
begin
if CLK'event and CLK = '1' then
State<= Nextstate;
end if;
end process;
end Table;
    

EE Lab 6 Wave Diagram 1

EE Lab 6 Wave Diagram 2