21 Apr 2017
Austin, Texas

### San Gennaro

San Marzano tomato sauce, sausage, peppadews, garlic, caramelized onions, scamorza, mozzarella di bufala, pecorino romano

### Pistachio Cannoli

Pistachio Cannoli with powdered sugar and pistachio pieces sprinkled on the ends

13 Nov 2016
Write a VHDL module for a 4-bit counter with enable that increments by different
amounts, depending on the control input C. If En = 0, the counter holds its state.
Otherwise, if C = 0, the counter increments by 1 every rising clock edge, and if C = 1,
the counter increments by 3 every rising clock edge. The counter also has an activelow
asynchronous preset signal, PreN.

Part 1

```
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lab5_part1 is
port (CLK, PreN, En, C: in std_logic;
Qout: out std_logic_vector (3 downto 0));
end lab5_part1;
architecture counter of lab5_part1 is
signal Q: std_logic_vector (3 downto 0);
begin
Qout <= Q;
process (PreN, CLK)
begin
if PreN = '0' then Q <= "1111";
elsif CLK'event and CLK = '1' then
if En = '0' then Q <=Q;
elsif En = '1' and C = '0' then Q <= Q + 1;
elsif En = '1' and C = '1' then Q <= Q + 3;
end if;
end if;
end process;
end counter;
```

Part 2

```
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lab6_part2 is
port (X, CLK: in bit;
Z: out bit);
end lab6_part2;
architecture Table of lab6_part2 is
signal State, Nextstate: integer range 0 to 5:=0;
begin
process (State, X)
begin
case State is
when 0 =>
if X = '0' then Z <='0'; Nextstate <= 1;
else Z <= '0'; Nextstate <= 3; end if;
when 1 =>
if X = '0' then Z <= '0'; Nextstate <= 3;
else Z <= '0'; Nextstate <=2; end if;
when 2 =>
if X = '0' then Z <='0'; Nextstate <= 4;
else Z <= '0'; Nextstate <= 2; end if;
when 3 =>
if X = '0' then Z <= '0'; Nextstate <= 3;
else Z <= '0'; Nextstate <=5; end if;
when 4 =>
if X = '0' then Z <='1'; Nextstate <= 3;
else Z <= '0'; Nextstate <= 2; end if;
when 5 =>
if X = '0' then Z <= '1'; Nextstate <= 4;
else Z <= '0'; Nextstate <=2; end if;
end case;
end process;
process (CLK)
begin
if CLK'event and CLK = '1' then
State<= Nextstate;
end if;
end process;
end Table;
```

30 Oct 2016
Design a Mealy sequential circuit (Figure 16-27) which investigates an input sequence
X and will produce an output of Z = 1 for any input sequence ending in 1101 or 011.
Example:
X = 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0
Z = 0 0 0 1 0 1 1 0 1 0 0 1 0 1 0
Notice that the circuit does not reset to the start state when an output of Z = 1
occurs. However, your circuit should have a start state and should be provided with
a method for manually resetting the flip-flops to the start state. A minimum solution
requires six states. Design your circuit using NAND gates, NOR gates, and three D
flip-flops. Any solution which is minimal for your state assignment and uses nine or
fewer gates and inverters is acceptable. (Assign 000 to the start state.)
Test Procedure: First, check out your state table by starting in each state and
making sure that the present output and next state are correct for each input. Then,
starting in the proper initial state, determine the output sequence for each of the
following input sequences:
(1) 1 1 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1
(2) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 1 0 1

```
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity SM is
port(clk, rst, x: in STD_LOGIC;
Q1, Q2, Q3, Z: out STD_LOGIC
);
end SM;
architecture Structure of SM is
signal Vnet_0, Vnet_1, Q1p, Vnet_2, Vnet_3, Vnet_4, DB, Vnet_5, DC, Vnet_6,
Q3p, Xp, XpA, XpB, XpC, XpAp, BC, XpAC, XpBCp, Q2p: STD_LOGIC;
component nand2
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
C: out STD_LOGIC
);
end component;
component nand3
port (
A: in STD_LOGIC;
B: in STD_LOGIC;
C: in STD_LOGIC;
D: out STD_LOGIC
);
end component;
component inverter
port (
A: in STD_LOGIC;
B: out STD_LOGIC
);
end component;
component Dflipflop
port (
CLK: in STD_LOGIC;
D: in STD_LOGIC;
SN: in STD_LOGIC;
RN: in STD_LOGIC;
Q: out STD_LOGIC;
QN: out STD_LOGIC
);
end component;
begin
VHDL_Device_0: Dflipflop port map (clk, x,'1', rst, Vnet_1, Q1p);
VHDL_Device_1: Dflipflop port map (clk, DB, '1', rst, Vnet_5, Q2p);
VHDL_Device_2: Dflipflop port map (clk, DC, '1', rst, Vnet_6, Q3p);
VHDL_Device_3: inverter port map (x, Xp);
VHDL_Device_4: nand2 port map (Xp, Vnet_1, XpA);
VHDL_Device_5: nand2 port map (Xp, Vnet_5, XpB);
VHDL_Device_6: nand2 port map (Xp, Vnet_6, XpC);
VHDL_Device_7: nand2 port map (Xp, Q1p, XpAp);
VHDL_Device_8: nand2 port map (Vnet_5, Vnet_6, BC);
VHDL_Device_9: nand2 port map (XpAp, BC, DC);
VHDL_Device_10: nand2 port map (XpAC, XpBCp, Z);
VHDL_Device_11: nand3 port map (XpA, XpB, XpC, DB);
VHDL_Device_12: nand3 port map (Xp, Vnet_1, Vnet_6, XpAC);
VHDL_Device_13: nand3 port map (Xp, Vnet_5, Q3p, XpBCp);
Q1 <= Vnet_1;
Q2 <= Vnet_5;
Q3 <= Vnet_6;
end Structure;
```

18 Oct 2016
Design a counter which counts in the sequence that has been assigned to you. Use
D flip-flops and NAND gates. Simulate your design using SimUaid.
(b) 000, 011, 101, 111, 010, 110, (repeat) 000, . . .

11 Oct 2016
(a) Using a 3-to-8 decoder and two four-input OR gates, design a circuit that has
three inputs and a 2-bit output. The output of the circuit represents (in binary
form) the number of 1’s present in the input. For example, when the input is
ABC = 101, the output will be Count = 10. Write an entity-architecture pair to
implement a 3-to-8 decoder. Then write an entity-architecture pair for your circuit,
using the decoder as a component. Use the port definitions specified below.
For the 3-to-8 decoder:
port (a, b, c: in bit;
y0, y1, y2, y3, y4, y5, y6, y7: out bit);
For the main circuit: port (a, b, c: in bit; count: out bit_vector (1 downto 0));
(b) Simulate your code and test it using the following inputs:
a b c = 0 0 0, 0 1 0, 1 1 0, 1 1 1, 0 1 1

```
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity decoder is
port( a, b, c: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end decoder;
architecture arch1 of decoder is
begin
y0 <= (not a) and (not b) and (not c);
y1 <= (not a) and (not b) and c;
y2 <= (not a) and b and (not c);
y3 <= (not a) and b and c;
y4 <= a and (not b) and (not c);
y5 <= a and (not b) and c;
y6 <= a and b and not c;
y7 <= a and b and c;
end arch1;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity full_adder is
port(a, b, c: in std_logic; output: out std_logic_vector (1 downto 0));
end full_adder;
architecture arch2 of full_adder is
component decoder
port (a, b, c: in std_logic;
y0, y1, y2, y3, y4, y5, y6, y7: out std_logic);
end component;
signal z0, z1, z2, z3, z4, z5, z6, z7: std_logic;
begin
decoder0: decoder
port map (a, b, c, z0, z1, z2, z3, z4, z5, z6, z7);
output(0) <= (z1 or z2 or z4 or z7);
output(1) <= (z3 or z5 or z6 or z7);
end arch2;
```