09 Oct 2016
Just a quick warning, I got brunch with my friend’s parents and they literally ordered everything off the brunch menu. It was amazing.

Austin, Texas

### Potato Salad

Potato salad, crab, coddled egg, potato chips

### Pig Face Carnitas

Pretzel, pig face carnitas, fried egg puree, maple

### Cheddar Churros

Cheddar Churro, peanut butter, apple

### French Toast Fritter

French toast fritter, butternut, coffee mayo, feta

### Mesquite Bean Beignets

Mesquite bean beignets, peach jam

### Waffles and Crepes

Left:
Green chile waffle, chicken glaze, crispy skin, melon, chevre

Right:
Cornmeal crepe, duck ham, butternut puree, pear & shroom relish, beer pecan

### Duck Eggs and Sweet Potato Tots

Left:
Cast iron duck eggs, persimmon & olive, oyster shroom, charred squash

Right:
Sweet potato tots, chorizo verde, okra, soft scramble egg

### Chilaquiles

Chilaquiles, shrimp, green tomato pico, fried egg

### Eggplant Pancake

Eggplant pancake, pork belly, peach jam, jerk glaze, fried egg

### Tamale Benedict

Tamale benedict, black beans, poached egg, hollandaise

### Turkey Pot Pie and Sweet Potato Biscuits

Top and Bottom:
Turkey Pot Pie biscuits

Left and Right:
Sweet Potato biscuits

### Peach glazed and Chocolate Biscuits

Top and bottom:
Peach glazed biscuit

Left and Right:
Chocolate biscuits

### Spiced Bread Pudding

Spiced bread pudding, raisin, mexican vanilla ice cream

25 Sep 2016
Design an excess-3 code converter to drive a seven-segment indicator. The four
inputs to the converter circuit (A, B, C, and D in Figure 8-15) represent an excess-3
coded decimal digit. Assume that only input combinations representing the digits
0 through 9 can occur as inputs, so that the six unused combinations are don’tcares.
Design your circuit using only two-, three-, and four-input NAND gates and
inverters. Try to minimize the number of gates and inverters required. The variables
A, B, C, and D will be available from toggle switches.
Use (not ) for 6. Use (not ) for 9.
Any solution with 16 or fewer gates and inverters (not counting the four inverters
for the inputs) is acceptable.

```
library ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library SimUAid_synthesis;
use SimUAid_synthesis.SimuAid_synthesis_pack.all;
entity Lab3Circuit is
port(A, B, C, D: in STD_LOGIC;
S1, S2, S4, S5, S6, S7, S3, an1, an2, an3,
an0: out STD_LOGIC
);
end Lab3Circuit;
architecture Structure of Lab3Circuit is
signal Ap, Bp, Cp, Dp, CDp, CpD, X1, BpD, ApCDp, ACp,
X4, AD, BC, X7, X3, CD, X5, X6, X2: STD_LOGIC;
begin
VHDL_Device_0: inverter port map (A, Ap);
VHDL_Device_1: inverter port map (B, Bp);
VHDL_Device_2: inverter port map (C, Cp);
VHDL_Device_3: inverter port map (D, Dp);
VHDL_Device_4: nand4 port map (Ap, B, CDp, CpD, X1);
VHDL_Device_5: nand4 port map (CpD, BpD, ApCDp, ACp, X4);
VHDL_Device_6: nand4 port map (ACp, AD, BC, CpD, X7);
VHDL_Device_7: nand3 port map (Ap, Cp, D, X3);
VHDL_Device_8: nand3 port map (Ap, C, Dp, ApCDp);
VHDL_Device_9: nand2 port map (C, Dp, CDp);
VHDL_Device_10: nand2 port map (Cp, D, CpD);
VHDL_Device_11: nand2 port map (A, Cp, ACp);
VHDL_Device_12: nand2 port map (Bp, D, BpD);
VHDL_Device_13: nand2 port map (C, D, CD);
VHDL_Device_14: nand2 port map (A, D, AD);
VHDL_Device_15: nand2 port map (BpD, CpD, X5);
VHDL_Device_16: nand2 port map (ACp, CD, X6);
VHDL_Device_17: nand2 port map (Bp, Cp, X2);
VHDL_Device_18: nand2 port map (B, C, BC);
VHDL_Device_19: inverter port map (X1, S1);
VHDL_Device_20: inverter port map (X2, S2);
VHDL_Device_21: inverter port map (X4, S4);
VHDL_Device_22: inverter port map (X5, S5);
VHDL_Device_23: inverter port map (X6, S6);
VHDL_Device_24: inverter port map (X7, S7);
VHDL_Device_25: inverter port map (X3, S3);
an1 <= '1';
an2 <= '1';
an3 <= '1';
an0 <= '0';
end Structure;
```

18 Sep 2016
Design an excess-3 code converter to drive a seven-segment indicator. The four
inputs to the converter circuit (A, B, C, and D in Figure 8-15) represent an excess-3
coded decimal digit. Assume that only input combinations representing the digits
0 through 9 can occur as inputs, so that the six unused combinations are don’tcares.
Design your circuit using only two-, three-, and four-input NAND gates and
inverters. Try to minimize the number of gates and inverters required. The variables
A, B, C, and D will be available from toggle switches.
Use (not ) for 6. Use (not ) for 9.
Any solution with 16 or fewer gates and inverters (not counting the four inverters
for the inputs) is acceptable.

07 Sep 2016
### Hello!

Welcome to my website! My name is Joseph Bae and I am currently a third year student at the University of Texas at Austin!

05 Sep 2016
A combinational logic circuit has four inputs (A, B, C, and D) and one output Z.
The output is 1 iff the input has three consecutive 0’s or three consecutive 1’s. For
example, if A = 1, B = 0, C = 0, and D = 0, then Z = 1, but if A = 0, B = 1, C = 0,
and D = 0, then Z = 0. Design the circuit using one four-input OR gate and four
three-input AND gates.